A system is known in which transmission and reception of a high-speed digital signal are made using a synchronous communication network which uses optical fiber cables. In such a synchronous communication network, an oscillator is provided to generate a main clock within the system. This main clock is used in common on the transmitter end and the receiver end. Normally, a plurality of input signals are subjected to a hierarchical multiplexing process a plurality of times and converted into a high-speed multiplexed signal which is transmitted. The input signals are multiplexed in bytes. The signal speed increases every time the multiplexing takes place. For this reason, a circuit which operates at a high speed is necessary to carry out the multiplexing. Heat generated by a circuit which operates at the high speed is large, and the large heat generation makes it difficult to reduce the size of the equipment. Accordingly, in order to minimize the circuit scale, it is necessary to reduce the circuit parts which operate at the high speed and reduce the power consumption.
The SONET (synchronous optical network) is known as a high-speed transmission network using byte multiplexing. As shown in FIG. 1, an STS-1 signal of the SONET system has 8 bits in one byte and forms one frame in 90 bytes.times.9 columns.times.8 bits=6480 bits. One frame is 125 .mu.s, and the bit rate is 51.84 MHz. A frame format of the STS-1 signal shown in FIG. 1 is formed for every channel. 2 bytes at the head of the frame format are frame synchronizing patterns A1 and A2, and next one byte is a channel identification pattern C1. SOH (section overhead), LOH (line overhead) and POH (path overhead) are control data added to the information which is to be transmitted.
The plurality of STS-1 signals having the above described frame format are simply byte-multiplexed (no format conversion is made). FIG. 2 shows the byte multiplexing of 3 STS-1 signals. The STS-1 signals of the 3 S channels #1, #2 and #3 are byte-multiplexed to generate an STS-3 signal of 155.52 MHz. This STS-3 signal is standardized as an STM-1 signal according to the CCITT Recommendations. It is assumed that the STS-1 signals are transmitted as optical signals. The two bytes of frame synchronizing patterns A1 and A2 and one byte of channel identification pattern C1 are added to the head of the data of the three channels #1 through #3, and the STS-3 signal is formed by the byte multiplexing as indicated by dotted arrows. In this case, since insertion of the frame pattern or the like is not made as the STS-3 signal and the byte multiplexing is carried out so that the heads the channels #1 through #3 match, a frame multiplexed synchronizing pattern of the STS-3 signal is formed of six bytes.
In addition, the frame synchronizing patterns A1 and A2 of each of the channels #1 through #3 are the same, and patterns A1="11110110" and A2="00101000" are used. Further, the channel identification pattern C1 is selected to mutually different patterns among the channels #1 through #3.
Returning to FIG. 1, B1 through B3 are byte interleaving parities, C2 is a signal label byte indicating the existence/non-existence of information, D1 through D12 are data communication bytes for transferring status information or the like between equipment, E1 and E2 are order wire bytes, F1 and F2 are user channel bytes, G1 is a path status byte for detecting a parity error of a reception signal and for returning it to a far end equipment, H1 and H2 are pointers having variable slot function for fetching an asynchronous system, H3 is a pointer having variable slot function in stuffing, H4 is a multiframe indication byte, J1 is a trace byte, K1 and K2 are automatic protection switch bytes, and Z1 through Z5 are spare bytes.
On the receiver end, the frame synchronization is achieved by detecting the 6-byte frame multiplexed synchronizing pattern of the STS-3 signal shown in FIG. 2. As indicated by the dotted arrows, the data are demultiplexed into the data of the channels #1 through #3, and the channel identification pattern C1 is used to detect whether or not the multiplexing and demultiplexing are made correctly.
In addition, it is also possible to further multiplex a plurality of STS-1 signals. In this case, the frame synchronizing patterns Al and A2 and the channel identification pattern C1 at the head of the STS-1 signal are also byte-multiplexed to the head of the frame of the n multiplexed STS-n signal. The frame multiplexed synchronizing pattern which is added to the head of the STS-n signal in this case is formed of 2n bytes.
FIG. 3 is a block diagram showing a conventional digital signal multiplexing apparatus of the SONET system. The digital signal multiplexing apparatus shown has first through third multiplexing circuits 1 through 3, a multiplexing conversion circuit 5, a scrambler 6 and a parallel-serial conversion circuit 7. The first multiplexing circuit 1 multiplexes input signals 1. The input signals 1 are a group of signals from 28 subscriber's lines, for example. Input signals 2 and 3 which are supplied to the second and third multiplexing circuits 2 and 3 are similar to the input signals 1. The signals on each of the subscriber's lines are digitized. The first multiplexing circuit 1 multiplexes 28 digital signals of the input signals 1 in a multiplexer using a sub clock of 51.84 MHz, and makes a format conversion in a format converter to obtain the STS-1 signal. The STS-1 signals from the first through third multiplexing circuits 1 through 3 are supplied to an STS-3 multiplexing circuit 5 so as to obtain the STS-3 signal by a byte multiplexing. The STS-3 multiplexing circuit 5 has a multiplexing conversion circuit 6 for carrying out the byte multiplexing. The multiplexing conversion circuit 6 has serial-parallel converters 5-1 through 5-3, a parallel-parallel converter 5-4 and a scrambler 5-5. The STS-1 signals from the first through third multiplexing circuits 1 through 3 are converted into 8-bit (1-byte) parallel signals by the serial-parallel converters 5-1 through 5-3 using a clock signal of 6.48 Mbps and supplied to the parallel-parallel converter 5-4. The parallel-parallel converter 5-4 converts the 8-bit parallel signals from the first through third multiplexing circuits 1 through 3 into a 24-bit parallel signal, converts this 24-bit parallel signal into an 8-bit parallel signal using a clock of 19.44 Mbps and supplies the 8-bit parallel signal to the scrambler 5-5. In other words, the serial-parallel converters 5-1 through 5-3 and the parallel-parallel converter 5-4 are used to byte-multiplex the STS-1 signals. The scrambler 5-5 generates a pseudo random pattern from the main clock and scrambles the 8-bit parallel signal using the pseudo random pattern, so as to prevent a continuous generation of data "0" or "1" within the 8-bit parallel signal. In other words, the scrambler 5-5 adds the pseudo random pattern to the 8-bit parallel signal. The parallel-serial conversion circuit 7 multiplexes the scrambled 8-bit parallel signal in bytes and converts the signal into a serial signal of 155.52 MHz. This serial signal corresponds to the STS-3 signal described above. The serial signal is converted into an optical signal in an electric-optic converter which is not shown and is transmitted on an optical fiber.
Normally, the first through third multiplexing circuits 1 through 3 are independently made in the form of LSIs. The parallel-serial conversion circuit 7 is also made in the form of an LSI. The multiplexing conversion circuit 6 is integrated in the form of an LSI. Accordingly, the structure shown in FIG. 3 is made up of five LIS chips. Since the parallel-serial conversion circuit 7 operates at a high speed, the LSI of the parallel-serial conversion circuit 7 is ECL based while the LSIs of the remaining circuits are CMOS based.
However, the conventional circuit structure shown in FIG. 3 have the following problems. First, the scale of the apparatus is large. This is due to the fact that the multiplexing conversion circuit 5 is used to byte-multiplex the three STS-1 signals of 51.84 MHz to form the 8-bit parallel signal of 19.44 MHz. Originally, 155.5 MHz is obtained when the three STS-1 signals (51.84 MHz) are simply multiplexed, but this cannot be achieved by the LSI having the CMOS structure. Normally, the CMOS LSI can operate stably only up to approximately 50 MHz. But on the other hand, there is a demand to use the CMOS LSI as much as possible from the point of view of the power consumption and circuit scale. Hence, in order to satisfy this demand, the multiplexing conversion circuit 5 having the above-described structure is used to multiplex the STS-1 signals by the CMOS operation. However, the use of the multiplexing conversion circuit 5 makes the scale of the apparatus large.
Second, although the first through third multiplexing circuits 1 through 3 are made of the CMOS LSIs, these circuits process the signals of 51.84 MHz. As described above, the limit for ensuring stable operation on the CMOS LSI is approximately 50 MHz. For this reason, it is undesirable that the first through third multiplexing circuits 1 through 3 operate in a region exceeding the stable operating region.
On the other hand, the structure on the receiver end also has following problems. As described above, the frame multiplexed synchronizing pattern of the STS-n signal (n.gtoreq.3) has the 2n byte structure. Hence, it is necessary to employ a 2n byte pattern detection in order to detect the frame synchronization. As a result, there are problems in that the scale of the circuit becomes large as the multiplexing factor becomes large and the pull-in time of the synchronization becomes long. In addition, a synchronization error easily occurs due to the transmission error, and it is therefore necessary to increase the number of protection stages.